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| Preliminary Information SP5848 SP5848 2.2/1.3GHz 3-Wire Bus Dual Low Phase Noise PLL Preliminary Information DS5076 Issue 1.6 October 1999 Features G Ordering Information SP5848/KG/QP1S SP5848/KG/QP1T G G G Dual independent PLL frequency synthesisers in a single package, optimised for double conversion cable tuners, offering improved application 2.2GHz up-synthesiser optimised for low phase noise up to comparison frequencies of 4MHz 1.3GHz down-synthesiser optimised for low phase noise AND small step size Common reference oscillator and divider with independently selectable ratios for each synthesiser 10:1 programmable charge pump current ratio in up synthesiser 3-Wire bus programmable, each synthesiser indepently addressable Low power consumption, typ 100mW at 5V ESD protection, (Normal ESD handling procedures should be observed) Description The SP5848 is a dual PLL frequency synthesizer controlled by a 3-wire bus optimised for application in double conversion tuners. Each synthesiser loop within the SP5848 is independently addressable and contains an RF programmable divider, phase/frequency detector and charge pump/loop amplifier section; a common reference frequency oscillator and divider chain is provided, whose ratios for each loop are independently programmable. Both synthesisers are optimised for low phase noise performance and in addition synthesiser 2 is capable of operation with a low comparison frequency. G G G G Applications G TV, VCR, and cable tuning systems PUMP 1 11 BIT COUNT RF1 INPUT 16/17 4 BIT COUNT DRIVE 1 15 BIT LATCH 2 BIT LATCH DATA CLOCK ENABLE DATA INTERFACE 5 BIT LATCH 29 DIVIDE 2 BIT LATCH PORT P0 PORT P1 16 BIT LATCH 1 BIT LATCH PUMP 2 12 BIT COUNT RF 2 INPUT 16/17 4 BIT COUNT DRIVE 2 Figure 1 Block Diagram 1 SP5848 Preliminary Information PORT P1 CHARGE PUMP 2 DRIVE 2 Vee 2 RF2 INPUT RF2 INPUT Vcc2 CRYSTAL CRYSTAL CAP Vee PORT P0 CHARGE PUMP 1 DRIVE 1 Vee 1 RF1 INPUT RF1 INPUT Vcc1 ENABLE DATA CLOCK QP20 Figure 2 Pin Connections Electrical Characteristics o o Tamb= -40 C to +80 C, Vcc = 4.5 to 5.5 V, These characteristics are guaranteed by either production test or design. They apply within the specified ambient temperature and supply voltage unless otherwise stated. Characteristic Pin Min Supply voltage Supply current Synthesiser 1 (UP) RF1 input voltage RF1 input impedance RF1 division ratio Reference division 1 ratio Comparison frequency 1 Equivalent phase noise at phase detector 1 Charge pump 1 output current Charge pump 1 output leakage Charge pump 1 drive output current 7, 14 4.5 18 Value Typ Units Max 5.5 22 V mA Conditions 15,16 15,16 40 240 300 32767 mVrms 80 -2200MHz See Figure 4 See Table 1 4 -148 19 19 18 0.5 3 10 MHz dBc/Hz nA mA SSB, within loop bandwidth, all comparison frequencies See Table 3 Vpin 19=2V Vpin19 = 2V Vpin 18 = 0.7V 2 Preliminary Information SP5848 Electrical Characteristics (continued) o o Tamb= -40 C to +80 C, Vcc = 4.5 to 5.5 V, These characteristics are guaranteed by either production test or design. They apply within the specified ambient temperature and supply voltage unless otherwise stated. Characteristic Synthesiser 2 (DOWN) RF2 input voltage RF2 input impedance RF2 division ratio Reference division 2 ratio Comparison frequency 2 Equivalent phase noise at phase detector 2 Charge pump 2 output current Charge pump 2 output leakage Charge pump 2 drive output curent Data, clock and enable Input high voltage Input low voltage Input current hysterysis Clock rate Bus timing Data set up Data hold Enable setup Enable hold Clock to enable Reference Oscillator Crystal frequency External reference input frequency External reference drive Outputs ports P0 - P1 sink current leakage current 2 2 3 12,11,13 3 0 -10 0.8 11 300 600 300 600 300 8, 9 8 8 1, 20 2 10 mA A 2 2 0.2 16 20 0.5 500 Vcc 0.7 10 V V A Vpp KHz ns ns ns ns ns MHz MHz Vpp See Figure 6 for application Sinewave coupled through 10nF blocking capacitor Sinewave coupled through 10nF blocking capacitor See note 1 Vport = 0.7V Vport = Vcc 0.5 3 10 nA mA Pin Min 5,6 5,6 30 240 Value Typ Units Max 300 65535 See Table 2 16.25 -144 4000 KHz dBc/Hz Phase noise degrades above 250KHz SSB, within loop bandwidth, all comparison frequencie up to 250KHz See Table 4 Vpin 2=2V Vpin2 = 2V Vpin 3 = 0.7V mVrms 80 -1300MHz See Figure 5 Conditions All input conditions Note 1 Output ports high impedance on power up, with data, clock and enable at logic 0 3 SP5848 Absolute maximum Ratings All voltages referred to Vee at 0V Preliminary Information Characteristic Supply voltages RF1 input voltage RF2 input voltage All I/O ports DC offset Storage temperature Junction temperature Package thermal resistance chip to ambient chip to case Power consumption with all Vcc =5.5V ESD protection Min -0.3 -0.3 -55 Value Max 7 2.5 2.5 Vcc+0.3 +125 150 100 30 121 Conditions Units V Vp-p Vp-p V C C C/W C/W mW kV Differential Differential All ports off Mil std 883 latest revision methood 3015 class 1 2 Functional Description The SP5848 contains two PLL frequency synthesiser loops, each independently programmable from a 3-wire bus. The device is optimised for application in double conversion tuners where synthesiser 1 would form part of the upconverter and synthesiser 2 part of the down converter. Both loops are optimised for application in low phase noise loops and furtherly synthesiser 2 offers low comparison frequencies. A block diagram is contained in Figure 1. The device is programmed via a 3-wire bus where data is fed on serial data and clock lines and is gated by an enable line. Figure 3 indicates the format of the data. The sequence and timing of data load is described below in `programming mode' description. Each synthesiser is independently addressable and is defined by the LSB bit within the data transmission. A common reference frequency source and reference divider is used to derive the comparison frequency for both PLL loops. The reference division ratio is programmable via the data bus as defined in Tables1 and 2. The charge pump current for each loop is also programmable via the data bus as defined in Tables 3 and 4 Two switching ports are provided to control switching functions within the tuner. These ports also access test signals within the PLL as defined in Figure 7. Ports power up in high impedance state. Programming Mode The SP5848 is designed to be programmed from a standard 3-wire bus consisting of clock, data and enable, where the serial clock and data lines can be shared with other devices and the enable line is a unique line for individual device selection. To simplify programming each synthesiser is independently addressed, with the required loop being selected by the LSB bit , which functions as the address, therefore to fully program the device two complete data transmissions must be sent. The data format for each transmission is contained in Figure 3. Test modes as described in Figure 7, can be invoked by setting bit T0 in synthesiser 2 data word to a `1' and sending control data for bits T1-T2. In normal operation where T0 is set to a `0' bits T1 and T2 do not need to be transmitted 4 Preliminary Information SP5848 CLOCK ENABLE 222 P1 221 P0 220 CU1 2 19 CU0 2 18 RU2 217 RU1 216 RU0 215 MSB 21 LSB 20 `0' DATA Frequency data (15 bits) Synthesiser 1 control data CLOCK ENABLE DATA 224 T2 223 T1 222 T0 2 20 CD 219 RD2 218 RD1 217 RD0 216 MSB 21 LSB 20 `1' Frequency data (16 bits) Synthesiser 2 control data CU0 - CU1 RU0 - RU2 CD RD0 - RD2 T0 - T2 P0 - P1 : : : : : : Synthesiser 1 charge pump Synthesiser 1 reference division ration Synthesiser 2 charge pump Synthesiser 2 reference division ratio Test modes Switching ports P0 - P1 Figure 3 Control data 5 SP5848 Preliminary Information j1 j0.5 j2 j0.2 j5 0 0.2 0.5 1 2 5 80MHz 2j5 2j0.2 1GHz 1*7GHz 2*2GHz 2j2 2j1 2j0.5 Figure 4 Synthesiser 1 RF input impedance j1 j0.5 j2 j0.2 j5 0 0.2 0.5 1 2 5 80MHz 0*5GHz 0*9GHz 2j5 2j0.2 1*3GHz 2j0.5 2j1 2j2 Figure 5 Synthesiser 2 RF input impedance 6 Preliminary Information SP5848 RU2 0 0 0 0 1 1 1 1 RU1 0 0 1 1 0 0 1 1 RU0 0 1 0 1 0 1 0 1 Ratio 2 4 8 16 32 64 128 256 Table 1 Synthesiser 1 reference division ratio RU2 0 0 0 0 1 1 1 1 RU1 0 0 1 1 0 0 1 1 RU0 0 1 0 1 0 1 0 1 Ratio 4 8 16 32 64 128 256 512 Table 2 Synthesiser 2 reference division ratio CU1 0 0 1 1 CU0 0 1 0 1 Current (typical in mA) 0.12 0.26 0.55 1.2 Table 3 Synthesiser 1 charge pump current 7 SP5848 Preliminary Information CD 0 1 Current (typical in mA) 0.05 0.2 Table 4 Synthesiser 2 charge pump current Figure 6 Crystal oscillator application T2 X 0 0 1 1 T1 X 0 1 0 1 T0 0 1 1 1 1 Functional Description Normal operation Both charge pumps in sink mode Both charge pumps in source mode Port P1 = Fcomp1, P0 = Fcomp2 and charge pumps disabled Port P1 = (Fpd1)/2, P0 = (Fpd2)/2 X = dont care Figure 7 Test modes 8 http://www.mitelsemi.com World Headquarters - Canada Tel: +1 (613) 592 2122 Fax: +1 (613) 592 6909 North America Tel: +1 (770) 486 0194 Fax: +1 (770) 631 8213 Asia/Pacific Tel: +65 333 6193 Fax: +65 333 6192 Europe, Middle East, and Africa (EMEA) Tel: +44 (0) 1793 518528 Fax: +44 (0) 1793 518581 Information relating to products and services furnished herein by Mitel Corporation or its subsidiaries (collectively "Mitel") is believed to be reliable. However, Mitel assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual property rights owned by Mitel or licensed from third parties by Mitel, whatsoever. Purchasers of products are also hereby notified that the use of product in certain ways or in combination with Mitel, or non-Mitel furnished goods or services may infringe patents or other intellectual property rights owned by Mitel. This publication is issued to provide information only and (unless agreed by Mitel in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other information appearing in this publication are subject to change by Mitel without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user's responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to Mitel's conditions of sale which are available on request. M Mitel (design) and ST-BUS are registered trademarks of MITEL Corporation Mitel Semiconductor is an ISO 9001 Registered Company Copyright 1999 MITEL Corporation All Rights Reserved Printed in CANADA TECHNICAL DOCUMENTATION - NOT FOR RESALE |
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